Whileone Tech Space

Introduction As RISC-V expands into accelerator domains, software readiness becomes as critical as hardware innovation. This work focused on implementing a set of mathematical and BLAS primitives for a custom RISC-V architecture, forming foundational building blocks for numerical computing. The implementation included vector and matrix operations with careful attention to numerical correctness and floating-point behavior. Challenges and Constraints A key challenge was the abs

With the evolution of hardware design and development, two tools have become fundamental for those working on Instruction Set Architectures (ISA) QEMU and FPGA boards. Although both serve as key resources for developing, testing, and experimenting with different ISAs (such as RISC-V, ARM, x86, etc.), they operate in significantly different ways. This blog highlights the key distinctions between QEMU and FPGA boards and their use cases across various architectures. Key Featur

In this case study, we describe our systematic approach to benchmarking and validating workloads on FPGA platforms using HAPS (High-performance ASIC Prototyping System) models. The workflow involves compiling and cross-compiling a diverse set of workloads using both native QEMU and the open source toolchain, executing them on FPGA hardware, and capturing detailed performance metrics such as instructions executed and cycle counts.  1. Benchmark Preparation and Build Process W

The Problem statement: Our customer expressed their desire to know if Android (AOSP) was already ported by community to the RiscV platform and if we could provide a detailed summary of the current status of AOSP compilation/build and Qemu emulation progress for RiscV Introduction to AOSP: Android is an open source operating system for mobile devices and an open source project led by Google. Android Open Source Project (AOSP) repository offers the information and source code