Whileone Tech Space

Introduction As RISC-V expands into accelerator domains, software readiness becomes as critical as hardware innovation. This work focused on implementing a set of mathematical and BLAS primitives for a custom RISC-V architecture, forming foundational building blocks for numerical computing. The implementation included vector and matrix operations with careful attention to numerical correctness and floating-point behavior. Challenges and Constraints A key challenge was the abs

In this case study, we describe our systematic approach to benchmarking and validating workloads on FPGA platforms using HAPS (High-performance ASIC Prototyping System) models. The workflow involves compiling and cross-compiling a diverse set of workloads using both native QEMU and the open source toolchain, executing them on FPGA hardware, and capturing detailed performance metrics such as instructions executed and cycle counts.  1. Benchmark Preparation and Build Process W